True random number generation exploiting SET voltage variability in resistive RAM memory arrays

Abstract

A novel True Random Number Generator circuit fabricated in a 130nm HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.