Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT

Abstract

In single‐phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well‐known tool for designing advanced phase‐locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT‐based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half‐cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase‐locked loop (SRF‐PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT‐based SRF‐PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.