Shield Gate Trench MOSFET With Narrow Gate Architecture and Low-k Dielectric Layer

Abstract

A shield gate trench MOSFET (SGTMOS) featuring narrow gate (NG) architecture and low-k dielectric layer (LDL), namely NL-SGTMOS, is proposed in this letter. By eliminating the middle portion of gate polysilicon without additional mask, and employing LDL between control gate and the grounded field plate (FP), the NL-SGTMOS can greatly reduce parasitic gate-to-plate capacitance induced by the FP, which is a common issue in conventional SGTMOS structure. T-CAD simulations and experiments are performed for evaluations of the proposed device. The fabricated 1-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device (only with NG) achieved on-resistance of 4.57 mQ and gate charge of 7.46 nC at gate voltage of 10 V, which show progressive performance among other existing technologies.