Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications

Abstract

This work demonstrates the systematic methodology to optimize the negative capacitance (NC) n-type double gate (DG) junctionless (JL) device for low power (LP) and high-density (HD) applications. Results show that the positive charge density in the channel region of NCJL device induces negative internal gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</sub> ) at zero gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> = 0 V), which helps to deplete the channel and significantly reduces the off-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) compared to JL device. Conventional JL device requires a very high gate work function (φm ~ 5 eV) to achieve volume depletion. However, NCJL device can lower φm to mid-gap values while ensuring the full depletion in the channel and improving the on-current (Ion). NCJL device with mid-gap φm exhibits higher Ion and lower I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> compared to the performance target specified by International Roadmap for Devices and Systems (IRDS) for LP and HD applications.