Security and Communication Networks · 2019 · 24 citations · 3 references
ComputingComputer EngineeringComputer ScienceCryptographyHardware-software Co-designInternet Of ThingsBlock CiphersCryptographic ArchitectureCryptographic ImplementationEmbedded System SecurityHardware AccelerationLow-power Digital Circuit DesignApplication-specific Integrated Circuit Design MethodologyBlock Cipher DesignCode Size OptimizationExecution Time AnalysisHardware Acceleration For CryptographyLightweight Block CiphersLightweight CryptographyResource-constrained Devices
Recent lightweight block cipher competition (FELICS Triathlon) evaluates efficient implementations of block ciphers for Internet of things (IoT) environment. In the competition, the implementation of HIGHT block cipher achieved the most efficient lightweight block cipher, in terms of code size (ROM), memory (RAM), and execution time. In this paper, we further investigate lightweight features of HIGHT block cipher and present the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). By using proposed optimization methods, the implemented HIGHT block cipher shows better performance compared to previous state-of-the-art implementations.
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A Survey of Lightweight-Cryptography Implementations
Thomas Eisenbarth, Sandeep Kumar, Christof Paar et al. · IEEE Design & Test of Computers · 2007 · 477 citations
Implementation of HIGHT cryptic circuit for RFID tag
Young-Il Lim, Je-Hoon Lee, Younggap You et al. · IEICE Electronics Express · 2009 · 22 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +14