A 19.5% Efficiency 51–73-GHz High-Output Power Frequency Doubler in 65-nm CMOS

Abstract

This letter presents a 51-73-GHz high-output power and efficiency frequency doubler, which is fabricated in a standard 65-nm CMOS process. The proposed frequency doubler adopts a fourth-order transformer-based balun and a dual-LC tank network to achieve wideband operating at input and output ports. In addition, a common-source amplifier with a Gm-boosting technique is used as an output buffer to improve the output power and efficiency. The measured results show that the doubler achieves input and output return losses below -10 dB from 26 to 36 GHz and 53 to 80 GHz, respectively. The measured maximum gain is 0.8 dB at 66 GHz with 22-GHz 3-dB gain bandwidth at an input power of 1 dBm. Furthermore, with an input power of 7 dBm, the proposed doubler also exhibits a high efficiency of 19.5% and an output power of 5.7 dBm at 66 GHz. The dc power consumption is 14 mW with 1-V power supply, and the chip size is 0.63×0.52 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all test pads.