Publication | Closed Access
Multiple Layout-Hardening Comparison of SEU-Mitigated Filp-Flops in 22-nm UTBB FD-SOI Technology
22
Citations
24
References
2019
Year
Seu-mitigated Filp-flopsEngineeringVlsi DesignComputer ArchitectureHardware SecurityPhysical Design (Electronics)Advanced Packaging (Semiconductors)Flip-flop CellsElectronic PackagingHardened DffsElectrical EngineeringHardware ReliabilityFlash MemoryComputer EngineeringMicroelectronicsSilicon DebuggingMultiple Layout-hardening ComparisonApplied PhysicsStandard DffSemiconductor Memory
The standard and layout-hardened D filp-flops (DFFs) named DFF1-6 were designed and manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. Heavy-ion irradiation results indicate that FD-SOI technology has contributions to radiation hardness and the hardened DFFs have higher single-event upset (SEU) tolerance than the standard DFF. The upsets induced by the embedded SET targets are strongly dependent on the testing frequency. The layout separating the dual interlocked storage cell (DICE) structure can prevent the direct occurrence of SEU in flip-flop cells, and upsets were removed completely in two-fold DICE structure DFFs.
| Year | Citations | |
|---|---|---|
Page 1
Page 1