8.5 A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications

Abstract

To provide more vivid perception, TV resolution is increasing dramatically. In addition, 3D video is emerging because it can present immersive and complete scenes. Therefore, multiview video coding (MVC) is currently being developed as an extension of H.264/AVC [1]. Disparity estimation (DE), which effectively exploits the inter-view redundancy and reduces bit rates 20 % to 30%, is the most significant feature. However, DE and motion estimation (ME) require ultra-high computation and memory access. To encode a 3-view 1080p video, 82.4TOPS computing power and 54.6TB/s memory access are required with a full search algorithm. Moreover, view scalability is a critical functionality to deal with various MVC structures. There are 3 challenges to design an efficient MVC encoder chip: 1) Encoding high-definition (HD) multiview video requires high processing capability. 2) Conventional macroblock (MB) pipelining and scheduling cannot deal with various MVC structures. 3) With 3D and quad HDTV specifications, conventional ME architectures require 2.9Mb on-chip SRAM and 13.8GB/s