COMPCON · 1997 · 10 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsLow-power Cache DesignPower ManagementPower-aware DesignProcessor Core DesignProcessor MicroarchitectureSuperscalar ProcessingLow-power Instruction Cache DesignLow-power MicroarchitectureLow-power Processor DesignSuperscalar MicroarchitectureThermal-aware Core DesignThermal-aware DesignThermal-aware MicroarchitectureThrottling
This microprocessor is a the third generation PowerPC microprocessor and is a member of the G3 family of PowerPC processor products. Although it’s high performance (estimated 10.0 SPECint95) makes it suited for high end desktop systems, it’s low typical power dissipation of 5W and size of 66.5mm2 make it very attractive for portable systems as well. This microprocessor is a dual-issue superscaler machine with a four stage pipeline, separate Instruction and Data side Ll caches (32KB each), and full tags and support for up to a IMB of back-side L2. A Thermal Assist Unit and I-cache Throttling feature are included in the microprocessor as additional tools for thermal management. This microprocessor was designed in a 0.25um CMOS process (0.1 8um Leff) to operate at a frequency of 250MHz.
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Branch Prediction Strategies and Branch Target Buffer Design