IEEE Transactions on Device and Materials Reliability · 2019 · 24 citations · 26 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingFault-tolerant SystemsFault Tolerance DesignHardware Fault ToleranceRadiation HardeningFault SimulationLatch DesignLatchesRadiation-hardened Digital Circuit DesignRadiation-hardened Integrated CircuitsRadiation-hardening TechniquesRule-based Design AnalysisSingle Event Effects
Many radiation hardened by design (RHBD) latch architectures have been presented in the literature. These architectures are designed such that these can tolerate a charged particle impact at multiple nodes of the latch. These architectures differ in terms of approach for developing single event upset (SEU) tolerance, area and other parameters. The literature survey and SEU fault simulation study reveal that some of the architectures have SEU critical internal node pairs while most of the architectures exhibit single point failure at input data node. In this work, SEU mechanisms in RHBD latches are analyzed and a new rule-based design is proposed for designing latches which can tolerate multiple nodes upset. Critical charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Q}_{crit}$ </tex-math></inline-formula> ) of the proposed latch architecture is found significantly higher than most of double node upset tolerant latches published. Area requirement, power consumption, and performance of the proposed latch are found comparable with the latches of same class. The proposed rule-based design methodology may become helpful in developing a computer-aided design tool for synthesis of multiple nodes upset tolerant latch.
26