Novel Hybrid CMOS/Memristor Implementation of the AES Algorithm Robust Against Differential Power Analysis Attack

Abstract

Memory resistor or memristor is the fourth fundamental circuit element that has attained considerable attention due to its unique characteristics and possible extensive applications in future generation nanoscale circuits and systems. In this brief, the contribution that memristor-based circuits may offer to the evolution of cryptographic hardware and embedded systems is discussed. Specifically, it will be shown how memristor-based implementation of security algorithms can mitigate the danger of differential power analysis attacks (DPAs) at the technology level with lower cost and energy compared to conventional existing algorithmic countermeasure techniques. A 128-bit Advanced Encryption Standard (AES) cryptoprocessor was designed and implemented in both CMOS and hybrid CMOS/memristor technology. The robustness of the CMOS-based implementation against power analysis attacks was evaluated on Side-Channel Attack User Reference Architecture (SAKURA-GII) while the nanoscale counterpart system was evaluated by using a customized simulation and attack environment which was developed for extracting power traces using Synopsys and Cadence tools along with a DPA attack software implemented in MATLAB. It was observed that hybrid CMOS/memristor-based implementation provides considerable improvement over implementation with regular CMOS architectures in terms of energy consumption and attack tolerance and demonstrates good potential in mitigating DPA attacks without having to apply costly countermeasures such as masking or hiding.