IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2016 · 29 citations · 30 references
EngineeringComputer EngineeringComputer ScienceDigital CommunicationFault-tolerant ComputingParallel ComputingChannel CapacityChannel CodingCoding TheoryErasure CodingError Control CodingError CorrectionAdditive White Gaussian Noise ChannelArea EfficiencyArea-efficiency TradeoffsCommunication ChannelsDecoder DesignDecoding ComplexityOverhead ReductionPolar Codes
Polar codes are of great interest, since they are the first provably capacity-achieving forward error correction codes. To improve throughput and to reduce decoding latency of polar decoders, maximum likelihood (ML) decoding units are used by successive cancellation list (SCL) decoders as well as SC decoders. This paper proposes an approximate ML (AML) decoding unit for SCL decoders first. In particular, we investigate the distribution of frozen bits of polar codes designed for both the binary erasure and additive white Gaussian noise channels, and take advantage of the distribution to reduce the complexity of the AML decoding unit, improving the throughput-area efficiency of the SCL decoders. Furthermore, a multimode (MM) SCL decoder with variable list sizes and parallelism is proposed. If high throughput or small latency is required, the decoder decodes multiple received words in parallel with a small list size. However, if error performance is of higher priority, the MM-SCL decoder switches to a serial mode with a bigger list size. Therefore, the MM-SCL decoder provides a flexible tradeoff between latency, throughput, and error performance at the expense of small overhead. Hardware implementation and synthesis results show that our polar decoders not only have a better throughput-area efficiency but also easily adapt to different communication channels and applications.
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