2018 · 35 citations · 13 references
EngineeringComputer EngineeringComputer ScienceLow-power DesignMachine LearningSystem-on-chip DesignAccelerator ArchitectureDeep LearningHardware AccelerationNetwork-on-chip DesignNeural NetworksPower ManagementAcceleratorsDeep Learning AcceleratorsEnergy ConsumptionEnergy-efficient ArchitectureEnergy-efficient Hardware AccelerationNetwork-on-chipPower-efficient Accelerator DesignPower-efficient Architecture
Contemporary Deep Neural Network (DNN) contains millions of synaptic connections with tens to hundreds of layers. The large computational complexity poses a challenge to the hardware design. In this work, we leverage the intrinsic activation sparsity of DNN to substantially reduce the execution cycles and the energy consumption. An end-to-end training algorithm is proposed to develop a lightweight (less than 5% overhead) run-time predictor for the output activation sparsity on the fly. Furthermore, an energy-efficient hardware architecture, SparseNN, is proposed to exploit both the input and output sparsity. SparseNN is a scalable architecture with distributed memories and processing elements connected through a dedicated on-chip network. Compared with the state-of-the-art accelerators which only exploit the input sparsity, SparseNN can achieve a 10%-70% improvement in throughput and a power reduction of around 50%.
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Mastering the game of Go with deep neural networks and tree search
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Deep Speech 2: End-to-End Speech Recognition in English and Mandarin
Dario Amodei, Rishita Anubhai, Eric Battenberg et al. · arXiv (Cornell University) · 2015 · 2.2K citations · Full text