A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition

Abstract

A 0.42 to 3.45 Gb/s counter-based referenceless clock and data recovery (CDR) circuit that has an unrestricted and continuous-rate frequency acquisition capability is presented. The proposed frequency detector first selects a frequency driving direction of the recovered clock using counters and the frequency locking is achieved with the frequency driving direction plus phase information. After that, phase locking is done with the phase-locked loop. The CDR circuit occupied an area of 0.442 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using 180-nm CMOS process. Locking time less than 17.9 μs has been achieved from initially the highest data rate of 3.45 Gb/s to the lowest 0.42 Gb/s rate, and vice versa. The CDR circuit has shown 4.33-ps rms jitter in recovered data for a 3.45 Gb/s PRBS31 pattern. The power consumption is 20.3 mW including I/O buffer at 3.45 Gb/s with a 1.8-V supply.