2019 · 17 citations · 8 references
EngineeringElectrical EngineeringAnalog ElectronicsCircuit TheoryMicroelectronicsCmos Circuit DesignSmall-signal AnalysisTransient AnalysisTransient ResponseVoltage RegulatorsCapacitanceCmos Analog Circuit DesignLow-dropout Regulator DesignLow-dropout RegulatorsParasitic Capacitance CompensationPolesSettlingSettling Time
This paper presents a fast transient capacitorless low-dropout regulator (LDO). A Push-Pull Buffer (PPB) is proposed to drive the pass transistor. The low output resistance of the PPB allows the pole at the gate of the pass transistor to be pushed beyond the unity-gain frequency of the LDO regulation loop. Transient response is improved, the settling time of LDO are 0.2μS@CL=0pF and 1.14μS@C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> =100pF. The input transistors of error amplifier are realized Cascode structure which is used for connecting compensation capacitor CC. With this structure, RHP zero generated by compensation capacitor is pushed beyond the unity-gain frequency of the LDO regulation loop. And LHP zero generated by the CC is used to compensate the nondominate poles. Compensation capacitance is 1pF. The Dynamic Transient Improvement (DTI) circuit is adopted to reduce the ripples of the output voltage of LDO. The proposed LDO can operate from a supply voltage of 2.2V-4V with a minimum dropout voltage of 0.2V at a maximum 50mA load and quiescent current of 70μA. Only 4pF capacitor is integrated in the chip, the output of LDO can be connected 0100pF off-chip capacitor.
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