IEEE Transactions on Circuits & Systems II Express Briefs · 2019 · 16 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsOptoelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDifferential AmplifiersLow-noise Circuit DesignMixed-signal Integrated Circuit DesignOptical AmplifiersClock Data RecoveryCmos Analog Integrated CircuitsCmos Differential AmplifiersGain ControlGroup DelayNegative Capacitance Field-effect TransistorsReceiver DesignTransimpedance Amplifiers
A fully integrated 25 Gb/s low-noise optical receiver is presented which integrates transimpedance amplifier (TIA), continuous-time linear equalizer (CTLE), high-gain and highbandwidth limiting amplifier (LA), and clock and data recovery (CDR) circuit into a single die. The TIA employs an inverter-based pseudo-differential TIA scheme with input seriesinductor peaking, cross-coupled negative Gm pair and negative capacitance to improve the bandwidth, and noise performance, while a MOSFET corner compensation (MCC) circuit compensates for CMOS corner variations. A gain control (GC) scheme is proposed which solves the group delay issue caused by TIA input impedance variations from small input to overload current. Finally, a 2x-oversampling CDR using a bang-bang phase detector is included. The receiver is fabricated in 40-nm CMOS process, and the 850 nm VCSEL-based full-link measurement results show that the optical receiver achieves 44 μApp (RSSI Current = 43 μA, ER = 4.94 dB) optical modulation amplitude (OMA) sensitivity (BER<;1e-12) with 150 fF photodiode capacitance, from 3.3-V and 1.3-V supplies, respectively.
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