Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process

Abstract

Dynamic comparators owing to low-power, low-offset, and high-speed beneficiate in several low-power analog/mixed-mode applications. In this paper, a double-tail dynamic latch comparator is intended which exhibits low-offset with optimized power having relatively comparable speed. In this paper, equation for delay is also derived for the proposed dynamic latch comparator. The mismatch analysis and meticulous simulations for the proposed comparator are carried out in CADENCE SPECTRE at 1V supply voltage and 90-nm CMOS technology. It confirms that the reduced offset voltage is achieved with optimized power which is validated by 0.2k Monte Carlo simulation process. The simulation outcomes corroborate that the proposed dynamic latch comparator is 32% more power saving, 30% energy efficient and exhibits 69% less offset voltage in comparison to conventional double-tail dynamic latch comparator having 13% less die area and comparable speed of 148.23pS.