Reduction of the Hysteresis Voltage in Atomic‐Layer‐Deposited p‐Type SnO Thin‐Film Transistors by Adopting an Al₂O₃ Interfacial Layer

Abstract

Abstract The origin of hysteresis in the drain–source current ( I DS )–gate‐source voltage ( V GS ) characteristics of atomic‐layer‐deposited (ALD) p‐type SnO thin‐film transistors (TFTs) is examined by adding ALD Al 2 O 3 interfacial layers (IL) between the SnO channel layer and the SiO 2 gate insulator (GI) layer. SnO TFTs with SiO 2 GI exhibit a large hysteresis voltage ( V hy ) due to the trap state density near the interface between the SnO active layer and the SiO 2 GI (known as the border trap). Both experimental results and theoretical calculations show that the origin of border traps is the gap states in SiO 2 , which is induced by the Sn diffusion into the SiO 2 layer. The use of Al 2 O 3 films as ILs suppresses this diffusion. The effectiveness, however, is dependent on the thickness, crystallinity, and density of the Al 2 O 3 films. The V hy of the SnO TFTs can be decreased when the thickness and density of the ILs is increased if the amorphous structure of the Al 2 O 3 IL is maintained after the rapid thermal annealing process. p‐Type ALD SnO TFTs with optimum ILs exhibit a high on‐off ratio of I DS (1.2 × 10 5 ), high field‐effect mobility (1.6 cm 2 V −1 s −1 ), and a small V hy (0.2 V).