Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications

Abstract

A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for 2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer and 6-bit binary coding are adopted, utilizing switching-order shuffling in combination with dynamic element matching (DEM) to suppress the spurious tones owing to the current-source mismatch in three-dimensional FinFETs. In addition, output switches are designed to achieve make-before-break operation with the proposed low crossing point level shifter. Moreover, an output full-scale current trimming method is applied to maximize the power efficiency of the envelope-tracking (ET). The active area of a single DAC is 0.036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , its power consumption is 6.1 mW, and its SFDR is 80 dBc.