Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

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Engineering, Computer Engineering, Computer Science +17

Flow-through latch and edge-triggered flip-flop hybrid elements

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A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

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A 2.2 W, 80 MHz superscalar RISC microprocessor

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High-performance and low-power conditional discharge flip-flop

Peiyi Zhao, T. Darwish, Magdy Bayoumi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 189 citations

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