IEEE Transactions on Power Electronics · 2019 · 61 citations · 30 references
EngineeringElectrical EngineeringFault ToleranceFault-tolerant SystemsPower ElectronicsConverter TopologiesDevice ReliabilityMultilevel ConvertersPower QualityPower SystemsSemiconductor ReliabilityFault Tolerant OperationFault-tolerant Converter TopologiesHarmonic DistortionInverter SystemsMultilevel InvertersThree-phase InvertersTotal Harmonic DistortionTotal Harmonic Distortion Reduction
T-type multilevel (T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ML) inverters feature low total harmonic distortion and high efficiency. Reliability improvement is particularly important for T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ML inverters because they have high power device count. Methods that provide T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ML inverters with the ability to tolerate simultaneous failures of multiple switches in several legs have not been addressed in the existing literature. This paper proposes a redundant unit that can be shared across phases in a T-type three-level inverter topology to manage open-circuit faults in multiple legs. The redundant unit includes two switches and six diodes, with the extra active switches connected by diodes to each middle switch of the base inverter. Under fault conditions, a standby parallel leg consisting of middle switches and the added redundant devices can be formed in each phase of the inverter to provide an extra current path connecting the dc bus and loads. The middle switches can share the redundant unit simultaneously to replace faulted half-bridge switches. By these means, open-circuit faults in multiple legs can be tolerated simultaneously and the rated output capacity can be maintained during faulted operation. Experimental tests are given to verify the effectiveness and feasibility of this proposed fault-tolerant method.
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A Survey on Neutral-Point-Clamped Inverters
José Rodríguez, Steffen Bernet, P. Steimer et al. · IEEE Transactions on Industrial Electronics · 2009 · 1.8K citations