IEEE Transactions on Circuits and Systems I Regular Papers · 2019 · 21 citations · 10 references
EngineeringElectrical EngineeringAnalog ElectronicsDigital CommunicationVariable Rate TechnologyAnalog InstrumentationAnalog Integrated CircuitsDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersAutomatic Gain ControlDynamic RangeFinite Impulse Response FiltersGain ControlMixers
Time-interleaving analog-to-digital converters (ADCs) decrease the required sampling rate for one ADC to achieve giga samples per second (GS/s) rates. The gain and timing mismatches among the ADCs generate aliasing signals, degrading the spurious-free dynamic range of the time-interleaved ADC (TI-ADC). The conventional digital correction methods for TI-ADCs have not considered an application to direct-radio-frequency (RF) sampling receivers. We present a digital correction method for bandpass sampling four-channel TI-ADCs in the receivers. The proposed method, based on a correction method for two-channel TI-ADCs, reduces the in-band aliasing signals of the four-channel TI-ADCs by using in-phase/quadrature-phase (I/Q) downconversion mixers, cascaded integrator-comb (CIC) filters, and automatic gain control (AGC) in the receiver. This allows the correction circuit including mismatch estimation to have fewer building blocks than the conventional methods: seven adders, seven multipliers, and no finite-impulse-response filters. Simulations and measurements show that the proposed method reduces the aliasing signals of 1.2 GS/s 12-bit four-channel TI-ADCs to less than -80 dBFS.
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Simran Singh, Lauri Anttila, Michael Epp et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2015 · 60 citations
Engineering, Computer Engineering, Electrical Engineering +16