High-Frequency Quantum Well InGaAs-on-Si MOSFETs With Scaled Gate Lengths

Abstract

High-frequency InGaAs-On-Si MOSFETs with gate lengths down to 14 nm and a Si CMOS compatible fabrication flow are demonstrated. Record high combined ft and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 370 and 310 GHz, respectively, for III-V MOSFETs on Si is achieved. The key features include an InP/10 nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As/InP quantum well in the channel, as well as, self-aligned 8 nm thick source and drain spacers together with source and drain extensions, which minimize the parasitic access resistances due to the spacers. The use of the quantum well is shown to increase the electron mobility by a factor of three, resulting in a significant increase of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> due to a reduction of defect scattering at the gate oxide interface. The InP barrier is also shown to suppress the effect of border traps, through a reduction of the g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> frequency dispersion.