SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications

Abstract

We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with the gate of a conventional Si HK/MG MOSFET. Through optimization of the area ratio between the FE capacitor and the MOSFET, we show: 1) program/erase write voltages can be scaled down to logic compatible level, ±1.8 V, simplifying write circuitry; 2) write speed of 100ns; 3) write endurance cycles without degradation due to elimination of charge trapping in FE; 4) 2 bits/cell achieving software levels of accuracy for inference on MNIST training database; 5) state retention approaching 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s for a depolarization field of 0.3 MV/cm; 6) Multi-port (independent read and write) operations.