Automated Technology for Verification and Analysis · 2007 · 108 citations · 6 references
ComputingComputer EngineeringComputer ScienceAlgorithmsFormal MethodsTheory Of ComputationFinite State Machine ModelingLogic SynthesisModel TransformationReal-time Systems DesignSpecification LanguagesTemporal LogicAutomata SynthesisFinite-state Machine SynthesisFormal Verification For SynthesisLinear Temporal LogicLinear-time Temporal LogicTemporal Logic SpecificationTemporal Logic VerificationTree Automata
The bounded synthesis problem is to construct an implementation that satisfies a given temporal specification and a given bound on the number of states. We present a solution to the bounded synthesis problem for linear-time temporal logic (LTL), based on a novel emptiness-preserving translation from LTL to safety tree automata. For distributed architectures, where standard unbounded synthesis is in general undecidable, we show that bounded synthesis can be reduced to a SAT problem. As a result, we obtain an effective algorithm for the bounded synthesis from LTL specifications in arbitrary architectures. By iteratively increasing the bound, our construction can also be used as a semi-decision procedure for the unbounded synthesis problem.
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