2018 · 40 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputational NeuroscienceComputer ArchitectureMicroelectronicsIntegrated Circuit DesignMicroarchitecture DesignNear-threshold ComputingProcessor Core DesignSpiking Neural NetworksTiming AnalysisAsic ImplementationCommunicating Sequential ProcessesEmulationGate-level Timing SimulationNeuromorphic DevicesNeuromorphic HardwareSiliconStatic Timing Analysis
Intel's "Loihi" neuromorphic research chip implements spiking neural networks on 128 custom cores with 1024 neurons each. It supports a wide variety of algorithms inspired by computational neuroscience, notably on-chip learning. Loihi's design is specified in the Communicating Sequential Processes (CSP) language and implemented by an automated flow that generates two-phase bundled-data (BD) asynchronous pipelines with pulsed latch datapaths. This optimizes area and energy while using a mostly standard cell library and simplifies integration with synchronous collateral. The pre-silicon design was verified by static timing analysis, back-annotated gate-level simulation, and FPGA emulation. Tunable delay lines provide sufficient timing margin in extreme corners such as near-threshold-voltage. Loihi was manufactured in Intel's 14nm ASIC process in Q4 2017 and is functional from 0.55V to 1.25V.
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Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Mike Davies, Narayan Srinivasa, Tsung-Han Lin et al. · IEEE Micro · 2018 · 3.7K citations
Engineering, Computer Engineering, Computational Neuroscience +16
Click Elements: An Implementation Style for Data-Driven Compilation
A. Peeters, Frank te Beest, Mark de Wit et al. · 2010 · 96 citations