2019 · 146 citations · 40 references
EngineeringComputer EngineeringComputer ScienceField-programmable Gate ArraysMachine LearningReconfigurable ComputingDeep LearningField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationPattern RecognitionReconfigurable AcceleratorsAccuracyClassification AccuracyColumnsConvolutional Neural NetworksEnergy Utilization EfficiencyLayer PruningSystolic Array DesignSystolic Arrays
This paper describes a novel approach of packing sparse convolutional neural networks into a denser format for efficient implementations using systolic arrays. By combining multiple sparse columns of a convolutional filter matrix into a single dense column stored in the systolic array, the utilization efficiency of the systolic array can be substantially increased (e.g., 8x) due to the increased density of nonzero weights in the resulting packed filter matrix. In combining columns, for each row, all filter weights but the one with the largest magnitude are pruned. The remaining weights are retrained to preserve high accuracy. We study the effectiveness of this joint optimization for both high utilization efficiency and classification accuracy with ASIC and FPGA designs based on efficient bit-serial implementations of multiplier-accumulators. We demonstrate that in mitigating data privacy concerns the retraining can be accomplished with only fractions of the original dataset (e.g., 10% for CIFAR-10). We present analysis and empirical evidence on the superior performance of our column combining approach against prior arts under metrics such as energy efficiency (3x) and inference latency (12x).
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