A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

Abstract

This paper presents a 112 Gb/s PAM4 CMOS linear TIA to meet the requirements of emerging 400G Ethernet standards for data center interconnect. A regulated inverter-based amplifier with inductive shunt feedback is used to realize a high bandwidth, low noise front-end in 28 nm bulk CMOS process. A VGA accommodates input currents up to 1 mA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> with <;5% THD, and a 72 GHz post-amplifier chain delivers 300 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> output swing. The TIA provides 65 dBΩ trans-impedance gain with 4.7 μA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> input referred noise while dissipating 107 mW. Careful optimization of distributed inductive peaking ensures <;5 ps group delay variation over 45 GHz. Standalone electrical measurements verify the ability of the TIA to receive 112 Gb/s PAM4 data with an energy efficiency of 0.96 pJ/bit, showing the potential for single-chip CMOS transceiver solutions for next-generation data center applications.