A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs

Abstract

In this work we develop a compact model of ferroelectric field-effect-transistors (FeFET) for memory applications, enabling their exploration at the circuit and architecture level. In contrast to Landau-Khalatnikov (L-K) based approaches, the presented model is founded on the combination of a nucleation dominated multi-domain Presiach theory of ferroelectric switching with a conventional transistor model. The model successfully reproduces the evolution of the FeFET memory window as a function of the program and erase conditions (amplitude, pulse width, and history). To calibrate the model, we fabricated 10nm thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) MFM capacitors and FeFETs and characterized the polarization switching dynamics. Our results highlight the importance of accounting for the switching history, minor loop trajectory, and coupled time-voltage response of the ferroelectric to quantitatively reproduce the measured FeFET characteristics.