XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

TLDR

The paper introduces XNOR‑SRAM, a mixed‑signal in‑memory computing SRAM macro that performs ternary‑XNOR‑and‑accumulate operations for binary/ternary deep neural networks without row‑by‑row data access. The macro embeds ternary‑XNOR circuits in each bitcell, accumulates results on the read bitline by activating all 256 rows to form a resistive voltage divider, and digitizes the analog voltage with an 11‑level flash ADC. Prototype in 65‑nm CMOS delivers 403 TOPS/W and 88.8 % CIFAR‑10 accuracy at 0.6 V, representing 33× higher energy efficiency and 300× lower energy‑delay product than conventional digital hardware, and among the best energy‑efficiency/accuracy trade‑offs.

Abstract

We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated on the read bitline (RBL) by simultaneously turning on all 256 rows, essentially forming a resistive voltage divider. The analog RBL voltage is digitized with a column-multiplexed 11-level flash analog-to-digital converter (ADC) at the XNOR-SRAM periphery. XNOR-SRAM is prototyped in a 65-nm CMOS and achieves the energy efficiency of 403 TOPS/W for ternary-XAC operations with 88.8% test accuracy for the CIFAR-10 data set at 0.6-V supply. This marks 33× better energy efficiency and 300× better energy-delay product than conventional digital hardware and also represents among the best tradeoff in energy efficiency and DNN accuracy.