IEEE Solid-State Circuits Letters · 2018 · 29 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignProcess ControlCmos Circuit DesignControl SystemsDigital Integrated Circuit DesignFeedback ControlFrequency RegulationVoltage ScalingDroop ControlHysteresisOutput Voltage RegulationResponse TimeSettlingSettling TimeVoltageVoltage Scaling In Digital Circuits
We present a fully integrated digital low-drop-out regulator (LDO) with a 100-pF output capacitor (COUT) in 65 nm, based on hybrid-synchronous-asynchronous control. The goal is to minimize both response and settling time for abrupt load changes, which in turn enables the COUT scaling under a voltage droop constraint. The architecture is based on the synchronous proportional-integral feedback control in tandem with the asynchronous feedforward control. The asynchronous control loop employs load-event-based triggering, which compensates the output voltage immediately after a voltage droop, shortening response time. Then, the synchronous loop operates on either fast or slow clock selected automatically by a hysteresis control and quickly brings the output to the steady state, achieving short settling time. The proposed hysteresis control achieves superior stability and scales the lower bound of the slow-clock frequency by two orders over the existing scheme. The LDO prototype improves the responseand settling-time related metrics over the prior synchronous and asynchronous LDOs.
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