Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

Abstract

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-16</sup> J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.