LTD-Router: Low Latency Traffic Distributed FPGA Based Router Architecture Using Dedicated Paths

Abstract

Switch Allocation is an important pipeline stage in Network on Chip (NoC) routers. In this pipeline stage, input requests are assigned to output resources. A convenient router design should be able to resolve contradictions between the requests and available resources. One important issue that cramps routers and consequently NoC performance is head-of-line (HoL) blocking problem that only allows packets located at the head of a queue or Virtual Channel (VC) to be allocated by switch allocator. In this paper a new router architecture called LTD-Router is proposed that in addition to resolves HoL blocking problem, manages requests such that the packets with the same desired output, place in their appointed VC in a way that deadlock freedom is also guaranteed. Our router is also a better design in order to achieve low-latency and high throughput than the previous designs because it imposes lower area and timing overhead. The new design can be expanded to the most state-of-the-art routers. Evaluation results show that our LTD-Router can improve the network performance by reducing latency and improving throughput of the network by about 22%and 13%, respectively while its overhead imposition is about 21% lower than the previous designs.