Computing in memory with FeFETs

TLDR

Data transfer between processors and memory is a frequent bottleneck, and computing‑in‑memory (CiM) can reduce energy consumption and computational overhead by performing logic and arithmetic operations directly in memory, potentially improving application‑level performance. This paper presents a CiM architecture that employs ferroelectric field‑effect transistors (FeFETs). The FeFET‑CiM design functions as general‑purpose RAM and supports Boolean operations and word‑level addition using a single current reference in the sense amplifier, yielding a compact, low‑power implementation enabled by the high Ion/Ioff ratio of FeFETs and a voltage‑based sense scheme. Simulation case studies show that FeFET‑CiM achieves up to 119× speed‑up and 1.6× energy reduction over ReRAM and STT‑RAM CiM for 32‑bit addition, and delivers an average 2.5× speed‑up and 1.7× energy savings versus conventional non‑in‑memory approaches across diverse benchmarks.

Abstract

Data transfer between a processor and memory frequently represents a bottleneck with respect to improving application-level performance. Computing in memory (CiM), where logic and arithmetic operations are performed in memory, could significantly reduce both energy consumption and computational overheads associated with data transfer. Compact, low-power, and fast CiM designs could ultimately lead to improved application-level performance. This paper introduces a CiM architecture based on ferroelectric field effect transistors (FeFETs). The CiM design can serve as a general purpose, random access memory (RAM), and can also perform Boolean operations ((N)AND, (N)OR, X(N)OR, INV) as well as addition (ADD) between words in memory. Unlike existing CiM designs based on other emerging technologies, FeFET-CiM accomplishes the aforementioned operations via a single current reference in the sense amplifier, which leads to more compact designs and lower power. Furthermore, the high Ion/Ioff ratio of FeFETs enables an inexpensive voltage-based sense scheme. Simulation-based case studies suggest that our FeFET-CiM can achieve speed-ups (and energy reduction) of ~119X (~1.6X) and ~1.97X (~1.5X) over ReRAM and STT-RAM CiM designs with respect to in-memory addition of 32-bit words. Furthermore, our approach offers an average speedup of ~2.5X and energy reduction of ~1.7X when compared to a conventional (not in-memory) approach across a wide range of benchmarks.