Ultralow Defect Density at Sub-0.5 nm HfO₂/SiGe Interfaces via Selective Oxygen Scavenging

Abstract

The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO _x. This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO _x at the interface; the remaining ultrathin interlayer is consistent with a SiO _x-rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO _x-rich surface layer can produce an electrically passivated HfO₂/SiGe interface. To form this SiO _x-rich interlayer, metal gate stack designs including Al/HfO₂/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO₂-Al₂O₃) were investigated. As compared to the control Ni-gated devices, those with Al/HfO₂/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO _x-rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO₂ by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.