A 31 GHz 2-Stage Reconfigurable Balanced Power Amplifier with 32.6dB Power Gain, 25.5% PAE_max and 17.9dBm P_satin 28nm FD-SOI CMOS

Abstract

In this paper, a 31GHz reconfigurable balanced 2-stage power amplifier (PA) integrated in 28nm FD-SOI CMOS technology is demonstrated aiming for SoC implementation. Fine grain wide range power gain control with more than 10dB tuning range is enabled by body biasing feature while the design improves VSWR robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization over both stages. Maximum power gain of 32.6dB, PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 25.5% and Psat of 17.9dBm are measured, while robustness to industrial temperature range and process spread is demonstrated. This PA exhibits a maximum ITRS figure of merit of 26,925 which is the highest reported around 30GHz to authors' knowledge.