A 28GHz self-contained power amplifier for 5G applications in 28nm FD-SOI CMOS

Abstract

This paper presents a 28 GHz CMOS balanced Power Amplifier (PA) with integrated quadrature hybrid couplers to achieve robust load insensitivity for 5G phased array applications. The proposed balanced PA achieves a saturated output power (Psat) of 18.7dBm and a maximum Power Added Efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 12.4% with 17.5dB gain. It consumes 154mW and occupies 0.66mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Each power cell is based on class-AB Segmented Biased Push-Pull (SBPP) topology to improve both the AM-AM and AM-PM conversion. The circuit is implemented in 28nm UTBB FD-SOI CMOS technology taking, advantage of the back gate for threshold voltage adjustment.