A 256-QAM 39 GHz Dual-Channel Transceiver Chipset with LTCC Package for 5G Communication in 65 nm CMOS

Abstract

This paper presents a 39 GHz dual-channel transceiver chipset with LTCC package for 5G fixed wireless access (FWA) communication. The proposed transceiver chipset integrates two variable-gain frequency conversion channels, one LO chain and one SPI block. This chipset is fabricated in a standard 65 nm CMOS process. The TX results a maximum gain of 11 dB and a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 8.4 dBm, while the RX supplies a maximum gain of 52 dB, a NF of 5.4 dB and an OP1dB of 7.2 dBm. The single-channel communication link achieves an EVM of 3.72% for 64 QAM modulation and an EVM of 3.76% for 256 QAM modulation over 1 m distance.