2018 · 15 citations · 28 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksInterconnection NetworksCommunication NetworksLatency OptimizationMemory HierarchyMemory Hierarchy DesignMemory Hierarchy OptimizationNetwork Performance AnalysisCommunication InterfacesHigh-performance NetworkingLow-latency NetworkingMain Memory OrganizationMemory Access LatencyMemory Hierarchy PerformanceMemory LatencyMemory Scaling
Today 100GbE network interfaces are commercially available, with 400GbE proposals already in the standardization process. In this environment, a major bottleneck is DRAM latency, which has stagnated at 100ns per access. Beyond 100GbE, all packet sizes will arrive faster than main memory can accommodate, resulting packet drops due to the latency incurred by the memory hierarchy.
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