Uniformity Improvement of SiN<i> _x </i>-Based Resistive Switching Memory by Suppressed Internal Overshoot Current

Abstract

In this paper, we have investigated the effect of additional thin SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer on switching variability of SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based resistive memory (RRAM). We found that excessive LRS state generated in set operation results in large reset current and abrupt reset operation. The abrupt reset operation leads to large distribution of HRS. To investigate the transient characteristics of switching procedure in detail, measurement environment was implemented with equivalent circuit, and measured current from equipment was separated into capacitive and resistive current of resistive memory cell. Consequently, we point the internal overshoot current occurring in set operation as the cause of the excessive leaky state leading to large resistance distributions. Finally, we confirm the effect of low resistance state value (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LRS</sub> ) and cell capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DUT</sub> ) on the internal overshoot current of RRAM.