A 40 MHz clock and trigger recovery circuit for the CMS tracker fabricated in a 0.25 $\mu m$ CMOS technology and using a self calibration technique

Abstract

In the CMS central tracker, the LHC clock and the first level trigger decisions are distributed encoded as a single signal. This paper describes an ASIC for clock recovery and first level trigger decoding to be used in the tracker data acquisition and slow control systems. The IC was implemented in a 0.25 Pm CMOS technology using a rad-tolerant layout. It recovers the clock and trigger signals meeting the CMS tracker power budget and radiation hardness constraints. In the design of this ASIC a self-calibration techniques was adopted to accommodate for process parameters spread and device parameter changes due to radiation induced damage.