IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 56 citations · 24 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesClock GatingClock ManagementCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignTiming AnalysisClock Gating OptimizationHigh PerformanceHigh-speed TransmissionLatch DesignLatchesLow-power Latch DesignPower-delay ProductPower-delay Tradeoff
This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.
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