DRAM Retention at Cryogenic Temperatures

Abstract

The lack of memory operating at the temperature of cryogenic processors is generally seen as an obstacle for the realization of cryogenic computers, e.g. quantum computers (mK range) or computers utilizing Josephson junctions (around 4K). DRAM operated at a temperature between room temperature and the temperature of the CPU might be one possible memory solution. To utilize DRAM at cryogenic temperatures, understanding of its retention behavior is required. We have tested the functionality and retention behavior of unmodified commercially available DRAM parts at temperatures between 360K and 77K. All parts are functional in the temperature range. The retention time increases strongly when reducing the temperature from 360K to a temperature between 260K and 290K. At lower temperatures, all devices except one continue to show a small number of single cell retention fails. Activation energy analysis shows that the main distribution of retention are junction and subthreshold leakage. The residual fails occurring down to 77K are likely due to a tunneling process like gate-induced-drain leakage (GIDL). The number of these residual fails is small enough that redundancy or error correcting codes will make the use of DRAM at temperatures down to 77K feasible.