IEEE Solid-State Circuits Letters · 2018 · 11 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingDynamic Power ReductionMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsNonuniform SamplingQuantization
We propose a two-stage subranging-based nonuniform sampling (NUS) analog-to-digital converter (ADC) that preserves alias-free sampling and improves the effective voltage quantization resolution given the same number of comparators. The subranging architecture divides comparators into two stages (coarse and line); the voltage reference levels of the line stage are inserted between the coarse voltage reference levels in proximity to the input signal. A time-out mechanism is used to lilter out portions of nonuniformly sampled events while minimizing the impact on the lidelity of the reconstructed signal. A 65-nm CMOS prototype implements 15and 3-level voltage quantizers in the coarse and line stages, respectively, and achieves a spurious-free dynamic range 77 dB, an improvement of more than 15-dB compared to an 18-level flash-based NUS ADC with the same average sampling rate. The proposed architecture also reduces the hardware and the number of nonuniform samples by more than 2× when a flash-based NUS ADC architecture is utilized for the same effective voltage quantization resolution.
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