Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

TLDR

The paper introduces Neural Cache, a cache‑based architecture that transforms cache structures into massively parallel compute units for deep neural network inference. Neural Cache performs in‑situ arithmetic within SRAM arrays, maps data efficiently, minimizes data movement, and fully executes convolutional, fully connected, and pooling layers—including quantization—directly in‑cache. Experiments show Neural Cache reduces inference latency by up to 8.3× versus a Xeon E5 CPU and 7.7× versus a Titan Xp GPU, while boosting throughput 12.4× over CPU (2.2× over GPU) and cutting power use by 50% over CPU (53% over GPU).

Abstract

This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks. Techniques to do in-situ arithmetic in SRAM arrays, create efficient data mapping and reducing data movement are proposed. The Neural Cache architecture is capable of fully executing convolutional, fully connected, and pooling layers in-cache. The proposed architecture also supports quantization in-cache. Our experimental results show that the proposed architecture can improve inference latency by 8.3× over state-of-art multi-core CPU (Xeon E5), 7.7× over server class GPU (Titan Xp), for Inception v3 model. Neural Cache improves inference throughput by 12.4× over CPU (2.2× over GPU), while reducing power consumption by 50% over CPU (53% over GPU).