Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

TLDR

The study investigates and models a commercial 28‑nm bulk CMOS technology at cryogenic temperatures. The authors extract device parameters at 300 K, 77 K, and 4.2 K, develop a simplified‑EKV compact model and a body‑partitioning method, and validate a drift‑diffusion physics‑based model against measurements. The model shows that interface‑trap occupation degrades subthreshold swing at deep‑cryogenic temperatures, lowering the theoretical limit.

Abstract

This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteristics of this technology down to 4.2 K and to demonstrate the impact of cryogenic temperatures on the essential analog figures-of-merit. A new body-partitioning methodology is then introduced to obtain a set of analytical expressions for the electrostatic profile and the freeze-out layer thickness in field-effect transistors operating from deep-depletion to inversion. The proposed physics-based model relies on the drift-diffusion transport mechanism to obtain the drain current and subthreshold swing, and is validated with the experimental results. This model explains the degradation in subthreshold swing at deep-cryogenic temperatures by the temperature-dependent occupation of interface charge traps. This leads to a degradation of the theoretical limit of the subthreshold swing at deep-cryogenic temperatures.