Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Abstract

This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. This paper gives a detailed analysis for the reasons of poor linearity for passive-charge-sharing SAR ADCs and proposes solutions. The proposed ADC architecture with one-reference-cap-per-bit and short switches addresses the issue of signal-dependent reference voltage droop during SAR ADC bit trials and orthogonalizes the bit weights. The calibration technique presented further calibrates the ADC to 16-bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the digital-to-analog converter (DAC) capacitor array, the first reported in this type of SAR ADC. This paper provides the foundation of building a precision SAR ADC out of on-chip reference capacitors. Measurement result from a prototype test chip shows ±0.8 LSB (16-bit level) integrated non-linearity at 1 MSPS.