A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models

Abstract

Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.