A 36.3-to-38.2GHz −216dBc/Hz² 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter

Abstract

Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Performance limitations of conventional TDCs still remain a major roadblock for the adoption of high-frequency ADPLLs. To address this problem, this work introduces a noise-shaping TDC based on a 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order bandpass ΔΣ modulator (BPDSM) to achieve low integrated noise (183fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> ) and high linearity. Our approach enables low in-band phase noise (-85dBc/Hz @ 100kHz) for wide loop bandwidths (>1MHz) in a calibration-free single-loop digital 36.3-to-38.2GHz PLL. The prototype PLL effectively generates fast (500MHz/55μs) and precise (824kHz <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> frequency error) triangular chirps for FMCW radar applications.