Publication | Closed Access
A 40-Gb/s serial link transceiver in 28-nm CMOS technology
12
Citations
7
References
2014
Year
Unknown Venue
System On ChipSerdes OperatingChip-to-chip CommunicationVlsi DesignEngineeringMixed-signal Integrated CircuitComputer EngineeringComputer Architecture2-Tap Feed-forward EqualizersDigital Circuit DesignMicroelectronics28-Nm Cmos TechnologyElectronic Circuit
A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.
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